Minimization procedure in the design of digital systems

Representing that research resolves itself through development to beneficial application, this thesis proposes an advancement in the technique of economical logic design. While much work has been performed in perfecting implementation of hardware, existing methods fail to provide absolute minimality in all applications. The objective is to provide a procedure for the logic designer to develop solutions through rapid, error-free multi-comparison methods which provide minimal expression and the proof and record thereof. The presentation considers existing hardware, present minimization methods and their problems; develops examples describing the procedure and finally describes a computer program for economical reliable design. Time consuming calculations are eliminated through the development of graphical solutions by computer programs, rather than existing numerical methods of minimizing the Boolean expression. The approach reported here utilizes a combination of present methods, with new interpretations, to obtain minimized optimum circuitry - while simultaneously displaying the basic characteristics of the Boolean expression.