DESIGN AND SIMULATION OF HIGH SPEED LOW-POWER DUAL-MODE (NRZ/PAM4 12.8Gbps/25.6Gbps) SERIALIZER AND LASER DRIVER IN TSMC 65nm TECHNOLOGY
| dc.contributor.advisor | Chen, Jinghong | |
| dc.contributor.committeeMember | Peng, Jiming | |
| dc.contributor.committeeMember | Pei, Shin-Shem Steven | |
| dc.creator | Pendyala, Praveen Gayatree | |
| dc.date.accessioned | 2019-09-13T22:10:47Z | |
| dc.date.available | 2019-09-13T22:10:47Z | |
| dc.date.created | May 2017 | |
| dc.date.issued | 2017-05 | |
| dc.date.submitted | May 2017 | |
| dc.date.updated | 2019-09-13T22:10:47Z | |
| dc.description.abstract | This thesis presents the design and simulation of the schematic of a low-power (5.6pJ/b) dual-mode (12.8 Gbps NRZ, 25.6 Gbps PAM4) serializer with driver to be used in high-speed serial link transmitter application-specific integrated circuit (ASIC) to be employed in High-Energy Physics (HEP) experiments. The serializer and driver are being designed in a 65 nm CMOS technology. The ASIC itself will mainly include an LC-VCO phase-locked-loop (PLL), a 32:2 serializer and a CML driver. The driver also employs FIR pre-emphasis using a 2-bit programmable buffer delay chain. The serializer, driver and pre-emphasis are designed based on a combination of architectures presented in literature. A VCSEL model based on literature is designed using cadence schematic. Verilog-A module is instantiated to emulate the non-linear optical low-pass filtering response of a VCSEL and electrical components are built to form the electrical part of the VCSEL model. The schematic of the PAM-4/NRZ transmitter presented in this thesis is shown to have an energy efficiency of 5.6pJ/b (with serializer) and 3.71pJ/b (without serializer). Substantial improvements in vertical eye openings and jitter were recorded due to pre-emphasis. | |
| dc.description.department | Electrical and Computer Engineering, Department of | |
| dc.format.digitalOrigin | born digital | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | Portions of this document appear in: Feng, Y., J. Chen, Y. You, Y. Tang, Q. Fan, Z. Zuo, P. Pendyala, D. Gong, T. Liu, and J. Ye. "A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS." Journal of Instrumentation 12, no. 02 (2017): C02063. | |
| dc.identifier.uri | https://hdl.handle.net/10657/4557 | |
| dc.language.iso | eng | |
| dc.rights | The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. UH Libraries has secured permission to reproduce any and all previously published materials contained in the work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s). | |
| dc.subject | VCSEL | |
| dc.subject | Optical Link | |
| dc.subject | Transmitter | |
| dc.subject | Pre-emphasis | |
| dc.subject | Cmos | |
| dc.subject | 65nm | |
| dc.title | DESIGN AND SIMULATION OF HIGH SPEED LOW-POWER DUAL-MODE (NRZ/PAM4 12.8Gbps/25.6Gbps) SERIALIZER AND LASER DRIVER IN TSMC 65nm TECHNOLOGY | |
| dc.type.dcmi | Text | |
| dc.type.genre | Thesis | |
| thesis.degree.college | Cullen College of Engineering | |
| thesis.degree.department | Electrical and Computer Engineering, Department of | |
| thesis.degree.discipline | Computer and Systems Engineering | |
| thesis.degree.grantor | University of Houston | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |