DESIGN AND SIMULATION OF HIGH SPEED LOW-POWER DUAL-MODE (NRZ/PAM4 12.8Gbps/25.6Gbps) SERIALIZER AND LASER DRIVER IN TSMC 65nm TECHNOLOGY

This thesis presents the design and simulation of the schematic of a low-power (5.6pJ/b) dual-mode (12.8 Gbps NRZ, 25.6 Gbps PAM4) serializer with driver to be used in high-speed serial link transmitter application-specific integrated circuit (ASIC) to be employed in High-Energy Physics (HEP) experiments. The serializer and driver are being designed in a 65 nm CMOS technology. The ASIC itself will mainly include an LC-VCO phase-locked-loop (PLL), a 32:2 serializer and a CML driver. The driver also employs FIR pre-emphasis using a 2-bit programmable buffer delay chain. The serializer, driver and pre-emphasis are designed based on a combination of architectures presented in literature. A VCSEL model based on literature is designed using cadence schematic. Verilog-A module is instantiated to emulate the non-linear optical low-pass filtering response of a VCSEL and electrical components are built to form the electrical part of the VCSEL model. The schematic of the PAM-4/NRZ transmitter presented in this thesis is shown to have an energy efficiency of 5.6pJ/b (with serializer) and 3.71pJ/b (without serializer). Substantial improvements in vertical eye openings and jitter were recorded due to pre-emphasis.