A Strategy for Mapping Threads to GPUs in a Directive-Based Programming Model
| dc.contributor.advisor | Gabriel, Edgar | |
| dc.contributor.committeeMember | Chapman, Barbara M. | |
| dc.contributor.committeeMember | Johnsson, Lennart | |
| dc.creator | Shen, Chen 1988- | |
| dc.date.accessioned | 2017-06-30T21:11:50Z | |
| dc.date.available | 2017-06-30T21:11:50Z | |
| dc.date.created | May 2017 | |
| dc.date.issued | 2017-05 | |
| dc.date.submitted | May 2017 | |
| dc.date.updated | 2017-06-30T21:11:51Z | |
| dc.description.abstract | The proliferation of accelerators in modern clusters makes efficient coprocessor programming a key requirement if application codes are to achieve high levels of performance with acceptable energy consumption on such platforms. This has led to considerable effort to provide suitable programming models for these accelerators, especially within the OpenMP community. While OpenMP 4.5 offers a rich set of directives, clauses and runtime calls to fully utilize accelerators, an efficient implementation of OpenMP 4.5 for GPUs remains a non-trivial task, given their multiple levels of thread parallelism. In this thesis, we describe a new implementation of the corresponding features of OpenMP 4.5 for GPUs based on a one-to-one mapping of its loop hierarchy parallelism to the GPU thread hierarchy. We assess the impact of this mapping, in particular the use of GPU warps to handle innermost loop execution, on the performance of GPU execution via a set of benchmarks that include a version of the NAS parallel benchmarks specifically developed for this research; we also used the Matrix- Matrix multiplication, Jacobi, Gauss and Laplacian kernels for better understanding the potential performance issues. | |
| dc.description.department | Computer Science, Department of | |
| dc.format.digitalOrigin | born digital | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | Portions of this document appear in: Chen Shen, Xiaonan Tian, Dounia Khaldi, and Barbara Chapman, "Assessing One-to-One Parallelism Levels Mapping for OpenMP Offloading to GPUs," Proceedings of the 8th International Workshop on Programming Models and Applications for Multicores and Manycores (2017): 68-73. DOI: 10.1145/3026937.3026945 | |
| dc.identifier.uri | http://hdl.handle.net/10657/1857 | |
| dc.language.iso | eng | |
| dc.rights | The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. UH Libraries has secured permission to reproduce any and all previously published materials contained in the work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s). | |
| dc.subject | OpenMP | |
| dc.subject | OpenUH | |
| dc.subject | GPUs | |
| dc.title | A Strategy for Mapping Threads to GPUs in a Directive-Based Programming Model | |
| dc.type.dcmi | text | |
| dc.type.genre | Thesis | |
| thesis.degree.college | College of Natural Sciences and Mathematics | |
| thesis.degree.department | Computer Science, Department of | |
| thesis.degree.discipline | Computer Science | |
| thesis.degree.grantor | University of Houston | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |