Cost-effective Network Reordering using FPGA

Advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, requiring robust solutions in software and hardware to achieve low latency and high throughputs. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. One approach to solve this problem is to reorder packets using hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network entry point due to their high performance and flexibility. This research proposes a scalable hardware-focused method for reordering packets that can be fully synthesized to FPGAs with minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.