Cost-effective Network Reordering using FPGA
| dc.contributor.advisor | Chen, Yuhua | |
| dc.contributor.committeeMember | Chen, Jinghong | |
| dc.contributor.committeeMember | Zagozdzon-Wosik, Wanda | |
| dc.creator | Hoang, Vinh Q. | |
| dc.date.accessioned | 2023-06-04T21:02:39Z | |
| dc.date.created | December 2022 | |
| dc.date.issued | 2022-12-14 | |
| dc.date.updated | 2023-06-04T21:02:40Z | |
| dc.description.abstract | Advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, requiring robust solutions in software and hardware to achieve low latency and high throughputs. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. One approach to solve this problem is to reorder packets using hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network entry point due to their high performance and flexibility. This research proposes a scalable hardware-focused method for reordering packets that can be fully synthesized to FPGAs with minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip. | |
| dc.description.department | Electrical and Computer Engineering, Department of | |
| dc.format.digitalOrigin | born digital | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/10657/14440 | |
| dc.language.iso | eng | |
| dc.rights | The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s). | |
| dc.subject | FPGA | |
| dc.subject | IoT | |
| dc.subject | Reordering | |
| dc.subject | Network | |
| dc.title | Cost-effective Network Reordering using FPGA | |
| dc.type.dcmi | Text | |
| dc.type.genre | Thesis | |
| dcterms.accessRights | The full text of this item is not available at this time because the student has placed this item under an embargo for a period of time. The Libraries are not authorized to provide a copy of this work during the embargo period. | |
| local.embargo.lift | 2024-12-01 | |
| local.embargo.terms | 2024-12-01 | |
| thesis.degree.college | Cullen College of Engineering | |
| thesis.degree.department | Electrical and Computer Engineering, Department of | |
| thesis.degree.discipline | Computer and Systems Engineering | |
| thesis.degree.grantor | University of Houston | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science in Electrical Engineering |