Analog-To-Digital Data Converters in Bulk CMOS for Harsh Radiation and High Temperature Environment Applications

This dissertation focuses on analog-to-digital data converters for harsh environments. There is an increasing demand for reliable high temperature electronics implemented in low-cost bulk CMOS technologies. First, a detailed study of high temperature impairments is presented. An analytical model for small signal and large signal for the high temperature operation of MOSFET devices in 0.13 µm bulk CMOS process is then presented. A prototype has been made in 0.13 µm bulk CMOS. The I-V transfer characteristics have been measured at different temperatures from 25 °C to 200 °C. The experimental results are compared with the simulation results from the developed model to verify the reliability of the EDA tools at high temperature. Second, a scattered temperature sensor is presented that is employed in a high temperature ADC. The main challenges of on-chip CMOS temperature sensor front-ends are addressed and several techniques and architectures are proposed to improve performance. A prototype has been made in a 0.18 µm CMOS process. The measurement results are presented, which demonstrate good accuracy and performance. A temperature sensor is also used for the compensation method proposed in the continuous time sigma delta modulator. Third, a robust high bandwidth continuous time (CT) sigma delta ADC in 0.18 µm bulk CMOS technology for high temperature applications is presented. In order to enable operation in the intended application environment, a compensation method consisting of a temperature sensor has been proposed to compensate for the reduction. By sensing the temperature, the effective gm of the integrator is increased by stepping up the size of the input pair and the tail current of the operational amplifier. Simulations has been conducted in order to verify the validity of the proposed techniques. Finally, a radiation-hardened 10-bit 25 MS/s SAR ADC for harsh environments is presented. Different techniques have been studied. A Triple Modular Redundancy (TMR) technique has been used. The radiation-hardened ADC is implemented in 0.18 µm bulk CMOS. It achieves an ENOB of 9.4 bits under SEE.