Charlson, Earl J.2018-02-152018-02-15December 22012-12December 2http://hdl.handle.net/10657/2183A controller for an all digital phase locked loop which operates by pulse addition and removal is investigated. Being a first order system, the digital phase locked loop is more limited in regard to parameter controls than its second order analog counterpart. A loop with a fast lock time generally has poor phase/frequency accuracy, while a loop programmed for high accuracy will have slow lock time. Given that the digital phase locked loop is digitally programmable, a set of parameters may be selected which will minimize the lock time of the loop. Once the loop is locked, the parameters may be changed to alter the loop bandwidth and increase the loop accuracy. A controller circuit has been designed to adjust loop parameters in such a manner thereby optimizing loop performance. The exclusive-OR phase detector which is commonly used with the pulse addition/removal type digital phase locked loop has a phase lock range of plus or minus a quarter of a cycle. This work investigates the loop response to an incoming signal which is outside of the phase lock range of phase detector and inside the frequency lock range of the loop. A sub-circuit is proposed to improve the lock time of the loop when it encounters an incoming signal with these characteristics. The proposed circuits were designed using integrated circuit layout tools and submitted to a semiconductor manufacturer for fabrication. The controller concept and results of simulations and prototype experiments are presented.application/pdfengThe author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s).Digital Phase Locked LoopExclusive-OR Phase Detector2018-02-15Thesisborn digital