Cheng, Albert M. K.2014-02-132014-02-13December 22013-12http://hdl.handle.net/10657/516In this work, we propose a new dynamic migration (DM) heuristic method integrating dynamic voltage scaling (DVS), dynamic power management (DPM) and task migration in multi-core real-time systems which can feasibly balance the task load and reduce energy consumption during execution to achieve energy efficiency. Meanwhile, voltage scaling based dynamic core scaling (VSDCS) is presented for reducing leakage power consumption under low task load conditions. The framework used for the proposed methods is composed of a partitioner, a local earliest deadline first (EDF) scheduler, a power-aware manager, a dynamic migration module, and a dynamic core scaling module. The primary unit is the power-aware manager which controls the frequency for the power consumption and the voltage scaling based on the feedback of the dynamic migration module and the dynamic core scaling module. Simulation results show that the DM heuristic can produce further energy savings of about 3 percent compared with the closest previous work. That is (1-(1 - 8\%)x(1 - 3%))=11% energy saved with the new DM techniques. This work also greatly reduces the cost of task migration among the multi-core processors. The results show that VSDCS can achieve up to 33 percent of energy savings under low load conditions as compared with previous methods.application/pdfengThe author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s).Real-time systemsReal-time schedulingLow-power designEnergy-aware schedulingEnergy-aware systemsMulti-core processorsComputer science2014-02-13Thesisborn digital