Design techniques for more efficient sequential circuits

Two storage elements are studied; the Edge Triggered Flip-Flop and the Master/Slave Flip-Flop. The two storage units have unique properties which do not yield the more efficient designs with present synthesis techniques. Chapter 1 is devoted to the Edge Triggered Flip-Flop. Examples of Chapter 1 rival the most efficient trial and error designs. In many counter designs the counter may be either synchronous or asynchronous. The edge triggering design techniques allow the designer to make the decision between asynchronous or synchronous circuits. Chapter 2 is devoted to the Master/Slave Flip-Flop. The synthesis techniques utilize partition pair algebra to determine the relationship between the Master/Slave Flip- Flop and the problem. A realization is defined in terms of partition pairs and mapping blocks of partitions. Chapter 3 proposes an extension of Chapter 2 that could be used to subdivide a large machine into smaller machines.