New methods for fault detection and location in large combination circuits

In recent years the increased emphasis on fault diagnosis in making large digital circuits center around the lack of test points in LSI circuits, the need for efficient test procedures in the face of increasing network complexity, and the increased need for complete testing of digital circuit. Most works (1-10) so far published are economically feasible only for circuits of modest size-typically one hundred of gates. In contrast a 1974 digital cabinet is likely to contain thousands of gates. The present work is devoted to seeking efficient methods for deriving complete experiments for fault detection and fault location in large combinational circuits. In this thesis, two methods for fault detection and fault location for large combinational circuits are presented. Both methods are based on a technique of partioning the given circuit into a series of smaller subnetworks. The first method, a fault detection method is derived on a basis of fault equivalency among subnetworks. To implement this method a computer program has been written which provides a nearly minimal complete fault-detection test experiment for any (large) combinational circuits. Another way to expand the limit of the presently available fault location methods is to use a method which is a combination of fixed-scheduled and adaptive-scheduled experiments. This method which is referred to as the hybrid method is presented. it has the advantage of requiring less computation time compared to adaptive scheduled experiment and the advantage of requiring less memory space compared to fixed-scheduled experiment, and has been proven to be useful especially for large combinational circuit fault-location. Examples are given to illustrate the methods.