# A minimal probability of error threshold gate

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## Abstract

A threshold logic gate is a gate whose output is a function of its inputs which are weighted by scalars. The use of threshold logic gates to realize Boolean switching functions may result in a significant reduction in the number of gates required over conventional methods. However, since threshold logic gates have been found unreliable, their use has not been extensive. Several methods have been developed to increase the reliability of threshold gate realizations. For the most part, though, the methods are worst case design. A more meaningful design might be to use the threshold realization for which the probability of error of the circuit used is minimized. In so doing, the design is based upon the statistics of the actual circuit used. In this thesis, it is assumed that a linearly separable switching function exists and that the statistics of the weights and inputs are known. The random variables are assumed to be independent. Based upon these statistics the probability density function of the output of the gate is derived. The weights and threshold are then adjusted to find the realization which minimizes the probability of error. The weights and threshold are adjusted by means of a multi-dimensional search technique with the probability of error as the performance criterion. This search is made upon a portion of weight space and it is accomplished by means of a digital computer program. The threshold gate realizations which minimize the probability of error are discussed in Chapter V and compared to existing threshold gate realizations of the same functions. Based upon the results obtained, a method to increase the reliability of threshold gate networks is suggested.