Design and Calibration of High-Speed and Power-Efficient Flash ADC in FDSOI CMOS



Journal Title

Journal ISSN

Volume Title



High-speed analog-to-digital converters (ADCs) with medium resolutions find various wideband applications in wireline and wireless communications, radar systems, and electronic test instruments. While time-interleaved (TI) successive-approximation register (SAR) ADCs have been widely investigated to achieve low-power and high-speed performance, the large number of sub-ADC channels makes the TI-SAR architecture more susceptible to mismatches including offset and gain mismatches among the sub-ADC channels and timing skew of the clocks distributed to them. The objective of this dissertation is to investigate power-efficient high-speed flash ADCs while alleviating the timing skew and inter-channel mismatches. Flash ADC provides the highest conversion speed. However, the flash ADC requires a large number of comparators to carry out the quantization process. As the ADC resolution increases, the number of comparators increases exponentially, resulting in high-power consumption. To improve power efficiency while benefiting from the high-speed performance of the flash architecture, three flash ADCs are developed in this research, including an ADC with a partially active 2-stage comparison and 2× time-domain latch interpolation (TDI), a 2-way TI-flash ADC with voltage-domain interpolation, and a pipelined flash ADC with a ping-pong structure in the second stage. The first flash ADC employs a partially active 2-stage comparison and 2× TDI to reduce power consumption while avoiding PVT-sensitive calibrations, such as time reference and voltage reference calibrations. To enhance the conversion speed of the 2-stage structure, the stringent timing constraint is resolved by a 25%-75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%-75% duty-cycle clock are also analyzed. Fabricated in a 28-nm fully-depleted silicon-on-insulator (FDSOI) CMOS process, the 5-GS/s 6-bit ADC achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOMW) of 84.5 fJ/conv.-step. In the second work, a 2-way TI-flash ADC is developed, which employs dynamic comparators with a pre-amplifier stage to achieve 10 GS/s conversion speed for the sub-channel ADC and voltage-domain interpolation to reduce power consumption. Fabricated in a 28-nm FDSOI CMOS process, the 20-GS/s 6-bit 2-way TI-flash ADC achieves an SNDR of 31.2 dB and an SFDR of 38.5 dB at Nyquist frequency, respectively, while consuming 204 mW power. The FOMW is 344 fJ/conv.-step. To further increase the flash ADC speed, a pipelined flash ADC is also developed, where the first stage employs current-mode logic (CML) comparators to enhance the speed and the second stage employs a ping-pong structure with dynamic comparators to achieve high power efficiency. Designed in a 22-nm FDSOI CMOS process, the 15-GS/s 7-bit pipelined single-channel flash ADC achieves an SNDR of 41.34 dB and an SFDR of 49.36 dB at Nyquist frequency with a power consumption of 97.5 mW. The corresponding FOMW is 72 fJ/conv.-step. Furthermore, an on-chip comparator offset calibration approach based on a successive-approximation (SA) search algorithm and the FDSOI back-gate bias is developed to provide sufficient comparator offset calibration range while avoiding comparator speed degradation.



Comparator offset calibration, Flash ADC, FDSOI, Two-stage comparison, Time domain interpolation