Design and Calibration of Power-Efficient High-Speed SAR-Based ADCs



Journal Title

Journal ISSN

Volume Title



High-speed analog-to-digital converters (ADCs) with medium-to-high resolutions find wide application in test equipment, wireline transceivers and wireless communication systems. While the successive-approximation-register (SAR) ADCs gain popularity recently owing to the advancing technology nodes. The goal of this dissertation was to explore the possibilities of further enhancing the operation speed of SAR-based ADCs and simultaneously pushing the leading edge of ADC power efficiency. A commonly adopted approach to boosting the sampling rate of Nyquist ADCs is time-interleaving (TI), where the operations of multiple ADC channels are coordinated by a multi-phase clock to aggressively shorten the sampling period. Unfortunately, extra hardware and power overhead associated with multi-phase clock generation, multi-channel reference supply, data multiplexing and possibly signal buffering greatly limit the achievable efficiency of the ADC, especially with a large interleaving factor. In addition, interleaving errors resulted from channel mismatches undermines the linearity of the ADC and thus mandates complicated calibrations to maintain a decent accuracy. As such, power-efficient approaches to maximizing the conversion rate of single-channel ADCs are crucial for optimization of the overall architecture. To support this argument, three hardware prototypes with proposed architectures in 28-nm FDSOI have been fabricated and characterized with through measurements. The first prototype is a two-step partially interleaved SAR ADC with fast noise reduction technique based-on loop-unrolled conversion. The inter-stage gain is controlled by a background calibration mechanism to avoid linearity degradation. A test chip measures a Nyquist SNDR of 46.65 dB at 1 GS/s while dissipating only 2.1 mW. The second hardware implementation is a single-channel SAR ADC with a double-rate comparator. The proposed architecture improves the ADC conversion rate and considerably decreases the power consumption at the same time. Clocked at 550 MS/s, the prototype ADC achieves a SNDR of 51.6 dB, consuming a total power of 1.28 mW. This translates into the best power efficiency among previously reported ADCs with >300 MS/s sampling rate. Finally, a bypass-based opportunistic adaptive comparator offset calibration is proposed to acquire the full benefit of alternate-comparator acceleration. As demonstrated by an eight-time interleaved SAR ADC showing a 49.02-dB Nyquist SNDR with a total power consumption of 9.8 mW at 2.4 GS/s.



Analog-to-digital converter (ADC), successive-approximation-register (SAR) ADC, High speed, low power


Portions of this document appear in: Fan, Qingjun, and Jinghong Chen. "A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology." IEEE Solid-State Circuits Letters 2, no. 9 (2019): 99-102. And in: Fan, Qingjun, Runxi Zhang, Phaneendra Bikkina, Esko Mikkola, and Jinghong Chen. "A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator." In ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp. 193-196. IEEE, 2019. And in: Fan, Qingjun, and Jinghong Chen. "A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration." In ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp. 301-304. IEEE, 2019. And in: Fan, Qingjun, Yi Hong, and Jinghong Chen. "A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration." IEEE Journal of Solid-State Circuits (2020).