Implementation and evaluation of a threshold decodable code for error correction

dc.contributor.advisorSimpson, Richard S.
dc.contributor.committeeMemberBargainer, James D., Jr.
dc.contributor.committeeMemberWiginton, Carroll Lamar
dc.creatorWert, Rayfield Kenneth
dc.description.abstractThreshold decodable codes (Majority Logic Decodable Codes) are a class of codes that offer moderate improvement in error rate for random errors in a Gaussian channel. Decoders for these codes can be hardware implemented with logic elements that give speed and cost advantages over many other classes of error correcting codes. This thesis presents the design documentation and evaluation of a threshold decoder for a (73,45) block code. Logic elements of the Medium Scale Integration (MSI) class were used extensively and complexity projections are made for other codes implemented with similar elements and design techniques.
dc.description.departmentElectrical and Computer Engineering, Department of
dc.format.digitalOriginreformatted digital
dc.rightsThis item is protected by copyright but is made available here under a claim of fair use (17 U.S.C. Section 107) for non-profit research and educational purposes. Users of this work assume the responsibility for determining copyright status prior to reusing, publishing, or reproducing this item for purposes other than what is allowed by fair use or other copyright exemptions. Any reuse of this item in excess of fair use or other copyright exemptions requires express permission of the copyright holder.
dc.titleImplementation and evaluation of a threshold decodable code for error correction
dc.type.genreThesis College of Engineering Engineering, Department of Engineering of Houston of Science


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