Implementation and evaluation of a threshold decodable code for error correction

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1971

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Abstract

Threshold decodable codes (Majority Logic Decodable Codes) are a class of codes that offer moderate improvement in error rate for random errors in a Gaussian channel. Decoders for these codes can be hardware implemented with logic elements that give speed and cost advantages over many other classes of error correcting codes. This thesis presents the design documentation and evaluation of a threshold decoder for a (73,45) block code. Logic elements of the Medium Scale Integration (MSI) class were used extensively and complexity projections are made for other codes implemented with similar elements and design techniques.

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