Reducing memory references via effective register usage

Date

1985

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Abstract

In order to better utilize the greater possible number of on-chip registers in VLSI-technology processor chips, the memory access behavior of several programs was traced and analyzed. More registers, properly used, lead to a substantial reduction in the off chip memory accesses required by a program, thereby resulting in a significant performance speedup. This work concentrates on identifying an effective register allocation policy and exploring the relationship between the number of registers used and the consequent reduction in the number of memory accesses. Several different register allocation strategies have been applied to the trace data. It is shown from this analysis that a great number of the memory accesses produced when executing a program can be eliminated by a small increase over the typical number of registers. A simple, but effective allocation strategy, which achieves this reduction, is to allocate registers to data with short average interaccess distance.

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Keywords

Virtual computer systems, Integrated circuits--Very large scale integration--Design and construction, Computer storage devices

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