FPGA Prototyping Framework on ARROW SoCKit Board with Xillybus Interface and Standard FIFO

dc.contributor.advisorChen, Yuhua
dc.contributor.committeeMemberWolfe, John C.
dc.contributor.committeeMemberVipulanandan, Cumaraswamy
dc.creatorLin, Jih-Tsen
dc.creator.orcid0000-0002-1800-5411
dc.date.accessioned2018-03-12T19:33:50Z
dc.date.available2018-03-12T19:33:50Z
dc.date.createdDecember 2017
dc.date.issued2017-12
dc.date.submittedDecember 2017
dc.date.updated2018-03-12T19:33:50Z
dc.description.abstractField Programmable Gate Array (FPGA) has been a popular candidate in hardware acceleration for offloading compute-intensive tasks from the traditional microprocessors. Due to the parallel nature, algorithm functions implemented on FPGAs can provide acceleration and are more energy efficient than the software based counterparts on traditional processors. With the reconfigurability, design changes on FPGA do not induce additional Non-recurring engineering cost (NRE) in re-tooling or in device re-spins as in the case of application-specific integrated circuit (ASIC) designs. Furthermore, a system-on-chip (SoC) architecture that integrates traditional processors with FPGA fabrics enables a hybrid reconfigurable architecture that the FPGA may be re-purposed as needed on the fly. These advantages in FPGA applications inspire this thesis in presenting a prototyping framework for FPGA system development and testing on an Arrow SoCKit evaluation board. The framework utilizes the Xillybus data transport interface to handle data communications between the on-board ARM processor and the FPGA. This thesis further presents the data communications interface requirements as well as a transmission time analysis for data transfer between the host processor software application and the FPGA module. Analyzing the transmission time for 10 kilobytes of data, it shows the transmission time latency is stable in the sense that it varies within 6 microseconds. In addition, analyzing the transmission time for 20 bytes data shows that manually flushing the buffer is advantageous for sending small sized data packets on asynchronous streams.
dc.description.departmentElectrical and Computer Engineering, Department of
dc.format.digitalOriginborn digital
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10657/2907
dc.language.isoeng
dc.rightsThe author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s).
dc.subjectFPGA
dc.subjectFPGA system prototyping framework
dc.titleFPGA Prototyping Framework on ARROW SoCKit Board with Xillybus Interface and Standard FIFO
dc.type.dcmiText
dc.type.genreThesis
local.embargo.lift2019-12-01
local.embargo.terms2019-12-01
thesis.degree.collegeCullen College of Engineering
thesis.degree.departmentElectrical and Computer Engineering, Department of
thesis.degree.disciplineComputer and Systems Engineering
thesis.degree.grantorUniversity of Houston
thesis.degree.levelMasters
thesis.degree.nameMaster of Science
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