Design of a multiple-microprocessor architecture for a printer and a communication controller to interface it to the IEEE-488 bus
The interprocessor communication structure for a multiple processor implementation of a printer and IEEE- 488 interface controller are developed in a top-down approach. The system design and interprocessor communication structure is developed for the entire printer, along with the detailed design of the IEEE-488 interface module. The printer's architecture is modular, with a different processor module handling each of the three real-time interfaces of the printer- the mechanism interface, the operator interface, and the communication interface. This modularity allows both the hardware and the software of each module to be tailored to the specific requirements of the interface it is controlling. Furthermore, this modularity makes it possible to exchange one module for another with a different kind of real-time interface, without disturbing the rest of the system. One additional requirement of the interprocessor communication technique is that it must be suitable for use with a menu-driven operator interface. To set the programmable features of the printer the operator will make selections from a menu of choices printed on the paper. This allows an indefinitely long list of parameters to be programmed with only a small number of keys on the printer's control panel. And by having some intelligence built into the menu, the operator is relieved of the requirement of having to understand potentially complicated interrelations between programmable parameters. The printer's architecture is developed by first presenting a set of specific requirements which define what the system is expected to do. Processes are then identified which will meet the stated requirements, and the influence of factors such as speed and modularity on process identification is shown. Each process is then defined in detail, using precedence graphs to show parallel as well as sequential functions. Once the individual processes are defined, process interaction is then studied, by closely examining interactions between processes within and bordering on the IEEE-488 module. A notation is presented for reducing complex interactions into a manageable form. After the software structure has taken shape, the hardware on which it runs is developed. A three-processor, shared-memory, moderately coupled system is presented which meets the requirements. Interprocessor communication is both by message passing and by direct sharing of a character-oriented FIFO buffer. Hardware and software considerations for solving the mutual exclusion problem for direct-shared-memory communication are presented in detail, along with the requirements for orderly passing of messages. Finally, the detailed design is presented. The design of the hardware modules is shown on the block level, and the details of the shared-bus logic are presented. Software interactions between each pair of processes within and bordering on the IEEE-488 module are described.